1. Field of Invention
The present invention relates to a CMOS input/output control circuit. More particularly, the present invention relates to a CMOS input/output control circuit capable of tolerating a range of voltage inputs.
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional CMOS input/output control circuit. As shown in FIG. 1, the CMOS input/output control circuit 100 comprises a PMOS transistor 10, an NMOS transistor 20, a NAND gate 30, a NOR gate 40, an inverter 50, a buffer 60 and an input/output pad 70.
(1) When the CMOS input/output control circuit 100 functions as an output device, a high potential level is applied to the output enable signal lead. A low potential level appears at the output terminal of the NAND gate 30 and a low potential level appears at the output terminal of the NOR gate 40. Hence, the PMOS transistor 10 is switched on while the NMOS transistor 20 is switched off. Consequently, the input/output pad 70 is at a high potential level (source voltage V.sub.DD). Conversely, if a low potential level is applied to the output enable signal lead, a high potential level appears at the output terminal of the NAND gate 30 and the output terminal of the NOR gate 40. Hence, the PMOS transistor 10 is switched off while the NMOS transistor 20 is switched on. Consequently, the input/output pad 70 has a low potential.
(2) When the CMOS input/output control circuit 100 functions as an input device, a low potential level is applied to the output enable signal lead. Hence, the output terminal of the NAND gate 30 is at a high potential level and the low output enable signal after passing through the inverter 50 to the NOR gate 40 produces a low output potential level. Therefore, both the PMOS transistor 10 and the NMOS transistor are turned off. Consequently, signal to the input/output pad 70, whether the potential level is high or low, can be relayed to the buffer 60 and become an input signal for any internal circuit.
Under both circumstances, the CMOS input/output control circuit 100 is functional as long as the high potential is at the same level as the source voltage V.sub.DD. However, since the development of submicron (smaller than 0.15 .mu.m) VLSI fabrication technologies, required source voltage has dropped from 5 V to 3.3 V or 2.5 V.
FIG. 2 is a schematic cross-sectional view of a conventional CMOS transistor. According to fundamental CMOS processing concept, the n-well 12 must be coupled to the highest voltage level in the circuit. In other words, the n-well of the PMOS transistors must be coupled to the highest voltage. The p-substrate 22 of the NMOS transistor must be coupled to the lowest voltage or ground. The CMOS circuit operates normally within the input/output control circuit only when the aforementioned voltage connections are made.
However, if 5 V are applied to the input/output pad 70 when the source voltage V.sub.DD is at 3.3 V or 2.5 V, a PN junction current forward bias will flow in the n-well region shown in FIG. 2. This is because a higher voltage is applied to the input/output pad 70 the source voltage V.sub.DD. Hence, a leakage current i will flow from the drain terminal to the n-well and then return back to the voltage source V.sub.DD. Since the PMOS transistor may malfunction, a conventional input/output control circuit may fail when voltage applied to the input/output pad is higher than the source voltage V.sub.DD.